Flow for IC desinging.............

Before starting any project engineers collects the all functionality , working criteria (fr. ,power estimation ) that is called system specifications. This is a very important part of any project ,if all the specifications are clearly defined and documented then project will go on write path.

This is the basic flow for designing the integration circuit. That is mainly divide in to 2 parts .
*Front -end -> This is the portion where designer write codes for creating the circuit that can work as functionality. front end also devided in many parts for designing......

1> FUNCTIONAL DESIGNING--- in this portion engineers start coding for the desire circuit.

in this phase coding is done according to the functionality only. For coding many language are used as c , system c , vhdl , verilog.

2> LOGIC DESINGING--- In this portion engineers start to make the code competible to the circuit designs.

* Back -end ->

as shown in the above picture backend part also contain main devision and a very important part of the IC.

*First step to take netlist from the frontend part .netlist contain all the information of the design in circuit form(gate lavel means every design is converted in mux,flop,gates,thransistor).
after that design engineer have to optimize it according to the timing , power .

*Then layout team have to make a plan for the floorplanning on chip.during the floorplanning design considers some points as ->

a) pin and bumps locations.

b) aspect ratio.

c) congestion due to the placement of the logic blocks.

d) Timing constrains.

* Next work is to make the partition of the logic on the floor ,that is required for make the easy layout . in this partitioning flat design is converted in to the hereriary design and clock , power group.

* power planning is a important part of the chip designing . in this engineers make a plan for power signal . power is given by top most layers of the metels used in the chip implementation , because this have many advantages as --> low resistance , less congestion in routing , less power heating. for upper level of routing . power signals are distributed by using macro ring,trunks.

*For placement cell are placed according to the timing required, pin location and optimized routing . setup timing is taken care during placement of cells .

* CTS (clock tree synthesis)-- is very important part of the chip designing . CTS gives the information about the skew , setup and hold time violation . for optimization many techniques are used as increase buffer size, insert buffers, put flip flop in combinational logic. after CTS mainly hold time violation is resolved.

* Routing is done according to the routing algo. as HVH,VHV,centriod . In routing many metal layer used . upper metal have less resistance and large width then the lower metals .top level metal layers are used for power and clock distribution.

*DFM(design for manufacturing)--in this phase many filler.dummy cell are put due to make the smooth surface of the each metal layer . this work is done by the DFM tool at each metal layer level. now a days DFM is very important part of IC designing.

finally got the GDS II for making the mask for implementing the chip.