Low Power Techniques

Why low power is required in circuit ?
Answer so don't need this -->

• Packaging costs

• battery Size increase with the power .

• Power supply rail design .

• Chip and system cooling costs .

• Noise immunity and system reliability

• Battery life (in portable systems) .

• Environmental concerns .



Lets take a look at various low power techniques in use today

(a)Traditional Techniques

• Clock gating (designed carefully due to clock feedback , glitch sensitive )

• Power gating (more area used for sleep circuit but very useful technique )

• Variable frequency (multi fr. PLL is required and handling is tough job )

• Variable voltage supply (extra power regulator circuit is used )

• Variable device threshold

• Minimize capacitance by custom design


(b) architecture Techniques

• Use of sleep mode .

• Make partion of the circuit (like memory spilt in many blocks )

• Power efficient circuits

• Parallelism in micro-architecture



Which one of the above techniques are aimed at reducing Dynamic Power and Leakage Power

Dynamic Power Reduction

• Clock Gating

• Power efficient circuits

• Variable frequency

• Variable voltage supply

Leakage Power Reduction

• Minimize usage of Low Vt Cells

• Power Gating

• Back Biasing

• Reducing Dynamic Power

• Reduce Oxide Thickness

• Use FINFET’s

LIFECYCLE OF CHIP

I want to design a chip –
today I m thinking we are working in vlsi industry that cool but how mach we know about the full chip starting to end this article I m writing as par my knowledge .if u want to add some thing u are most welcome because this will help me also in my learning process . I m writing this blog to give info about vlsi (what ever I know ) but with that this is my learning ladder also . so feel free to
Give any suggestion or adding some thing …………..

If I want to design a chip for that I looks the things like
· What will be the functionality of the chip. What are the main functionality and what are the I can try for with main functionality ?

first will be why I m designing this (specification and advantage )


· What are the io interfaces I will use for interface?
· In how many Different functional unit will be better to have in design means how much flexibility will be in design?
· Which language will be better for writing the code . what are the diff. portion .is there any analog part also .is there any previous code that I can use in my design ?
· What will be the clock speed and power consumption ?
· How many type of clock will required ?
· What will be the die size?
· What are the tool required for this type of the design ?

These are some question which should be take care.

So finally be confidante I have decided to write the code . for that first I want to test the specification will it is possible for me to create a code that gives the required functionality ?
or to check how much difficult to write that thing ? I will be able to write this type of code !!!!!!

for that test I would like to write my code in functional oriented language like c if I m able to write a functional code then I will verified it by test bench .
if it works then will convert it to the HDL (hardware description language ) like VHDL ,Verilog
it depends upon the particular comfort but I like verilog because it is easier to learn and coding for fresher.
in VHDL we have little more control on circuit as I think .
then synthesis the code means convert the code in to the circuit . covert the logic in to the circuit by netlisting it and verified
is it my real circuit using FEV (formal equivalent verification )


the simulate it with the test benches .if that is verified
then come to the backend and with that pre si validation test also .
here we will start to check many things like – timing ,power consumption ,placement and floor planning of the circuit, means overall we can say that will this design work on silicon or not (are we working on the implementable circuit ) .

according to the requirement we changes the circuit that is called ECO (engineering order changes )
we will put some extra circuit in our design that will be used when u want to dig up the cause of bags after implementation on silicon like scan circuit and fib cells .

now come to layout that is the physical implementation of the circuit on the silicon . floor planning is the crucial step of that . in ASIC people used the standard cell for the implementation of layout that have more flexibility and precession then any pld cell or custom cell usages.
There is two part of the validation in design flow : one is pre si validation , second is the post si validation .
After completion of the circuit layout DFM is implemented for reliability and density .
During the layout many checks are there like DRC (design rule check , dependes upon the technology used ), RV (reliability verification ), DFM density check , antenna checks etc .

After completion of layout that is sent to the fabrication unit and mask is created according to the technology files .

this article give some over view of the vlsi flow……………………….