Low Power Techniques

Why low power is required in circuit ?
Answer so don't need this -->

• Packaging costs

• battery Size increase with the power .

• Power supply rail design .

• Chip and system cooling costs .

• Noise immunity and system reliability

• Battery life (in portable systems) .

• Environmental concerns .



Lets take a look at various low power techniques in use today

(a)Traditional Techniques

• Clock gating (designed carefully due to clock feedback , glitch sensitive )

• Power gating (more area used for sleep circuit but very useful technique )

• Variable frequency (multi fr. PLL is required and handling is tough job )

• Variable voltage supply (extra power regulator circuit is used )

• Variable device threshold

• Minimize capacitance by custom design


(b) architecture Techniques

• Use of sleep mode .

• Make partion of the circuit (like memory spilt in many blocks )

• Power efficient circuits

• Parallelism in micro-architecture



Which one of the above techniques are aimed at reducing Dynamic Power and Leakage Power

Dynamic Power Reduction

• Clock Gating

• Power efficient circuits

• Variable frequency

• Variable voltage supply

Leakage Power Reduction

• Minimize usage of Low Vt Cells

• Power Gating

• Back Biasing

• Reducing Dynamic Power

• Reduce Oxide Thickness

• Use FINFET’s