SRAM

SRAM

 

Static Random Access Memory [SRAM]


Static Random Access Memory retains information placed within its cells until the values are overwritten or the power is switched off. Since SRAM doesn’t need to be refreshed constantly, reading and writing to memory can occur continuously. This allows it to be much faster than DRAM, which needs to pause between memory accesses to refresh and ensure that its contents are retained. Cache is much faster than main memory because it is implemented using SRAM

                                                                  Memory hierarchy

 



Basic six transistor SRAM memory cell






Pmos left side is M1 ,Nmos connected to bit line is M2,Nmos left side down is M3.


Pmos right side is M4 ,Nmos connected to bit line # is M5,Nmos right side down is M6.

(A) WRITE OPERATION:


When want to write 1 then bit line 1 and bit line# 0 will be apply . For this there may be 2 cases .


1) If node A having 1 and node b having 0 then


There will be very less current pass though M5 ( word line be on first) and node b will get discharge fully and create strong 0 . it will be depends upon the size of the m6 and m5 .


There will be very less current pass though M2 ( word line be on first ) and node a will be recharge again to strong 1 .


2) If node a having 0 and node b having 1 then


(B) READ OPERATION: for read operation both bit line and bit line # will be precharge to 1, then


1) if node a having 1 and node b having 0 then voltage of the bit line # will decrease this much the it will be less then weaker 1 (because of the M5 resistance it will not be fully discharge ) ,then difference between the bit line and bit line # is measured by the sense amplifier . Sense amplifier should be capable to measure this voltage difference. Timing of prechanging and sense amplifier should be different so there should not be short path between precharge and sense amplifier .




SIZING OF SRAM: sizing depends upon the technology used and the timing of the circuit required. Normally the sizes of the transistors are like M3 >M2 >M1.




Bit Line Precharge: used to precharge the bit line and bit line # before the read and write circuit . for this 3 pmos are used and connected at the same point so this circuit can provide strong 1 (pmos passes stronger 1 ).


Column Decoder Mux: use segmented mux to decode the address to the word lines .


Done many stage if address is big . domino logic can be used for fast speed.



Write driver circuitry : used to write the reuired bit on the memory node .


Sense Amplifier: important block for the reading operation . differential amplifier is used . sense amplifier amplified the low voltage difference between bit line and bit line #.


So reading speed is depends upon the sense amp.

Logic Optimization Techniques

There are many phase during the VLSI Flow. During these phase some logic optimization techniques are used .These increase performance, speed and decrease power. Some of those are:

Optimization technique during the coding:


• Used of unsigned integer (if u know value will not go to be negative) because it take less memory location and faster execution.


• Don’t use the nested if else loop. It will increase the complexity of the circuit and will put the many mux after synthesis those are not good for the design.


• Don’t use the global variable in critical loops.


• Use of switch circuit help in optimization of the circuit.


• Use of blocking statement helps in the reduce the race conditions.


• Logic should be more sequentional. Clock control circuit.


• Cloning of the logic is helpful.


• Always pass a structure by reference never pass it as a parameter.


• Use recursive should be avoided.


• Use single dimensional array avoid multidimensional array.






Optimization technique during the sch design :


• Use of many low fan-out/in gates in place of the single high fan-out/in gate.


• Use of domino logic where more speed path required.


• Put the signal (which is coming late) near to the output .so critical path will be less.


• Divide the load if it is more. One single wire into two signals.


• Put the lower transistor size in n logic higher the upper because it is driving full load.


• Use the multi Vt cell for lower leakage.


• Use the pass gates for fast circuit but be careful for the leakage and other things so always put the invertors after the pass gate.










Optimization technique during the layout:


• Put more no of the tap so latch up will be less.


• Use the strapping for big drivers.


• Use the shielding for the more activated signal.


• Use the more decap cell near the sensitive circuit.


• Use of symmetisity in routing.


• For long routing use the higher metal layers.


• For the clock shielding put one side vcc and second side vss.


• Clock routing should be in upper metal layers.


these techniques are very use full for a good design .

DESIGN FOR SPEED

Hi,  this post is for the designing of high speed digital design . some concepts of fast current in wires and how to control that fast current for fast processing .
        CMOS technology is used in  the ic. because of many reasons like - less area , easy to fabriacate , low power consumption , fast speed , balanced circuits .

       there are many techniques for speed up  in design in data path and clock paths.
some are -

• put the buffer in critical path . buffer insertion will give many effect in path . it will increase the speed , change the slope of transation of voltage , will give the full swing , decrease the cross cap . 
•   inside the gate put the input (which have the probability of coming late ) near to output .so critical path will be less .
• put domino logic .
• increase the supply voltage where ever is high speed require . for this multivoltage cell are used .
• put the transistor near to the output that have probability of input coming late .
• no of level in a path should be according to the logical effort .

there are many more .............