Logic Optimization Techniques

There are many phase during the VLSI Flow. During these phase some logic optimization techniques are used .These increase performance, speed and decrease power. Some of those are:

Optimization technique during the coding:


• Used of unsigned integer (if u know value will not go to be negative) because it take less memory location and faster execution.


• Don’t use the nested if else loop. It will increase the complexity of the circuit and will put the many mux after synthesis those are not good for the design.


• Don’t use the global variable in critical loops.


• Use of switch circuit help in optimization of the circuit.


• Use of blocking statement helps in the reduce the race conditions.


• Logic should be more sequentional. Clock control circuit.


• Cloning of the logic is helpful.


• Always pass a structure by reference never pass it as a parameter.


• Use recursive should be avoided.


• Use single dimensional array avoid multidimensional array.






Optimization technique during the sch design :


• Use of many low fan-out/in gates in place of the single high fan-out/in gate.


• Use of domino logic where more speed path required.


• Put the signal (which is coming late) near to the output .so critical path will be less.


• Divide the load if it is more. One single wire into two signals.


• Put the lower transistor size in n logic higher the upper because it is driving full load.


• Use the multi Vt cell for lower leakage.


• Use the pass gates for fast circuit but be careful for the leakage and other things so always put the invertors after the pass gate.










Optimization technique during the layout:


• Put more no of the tap so latch up will be less.


• Use the strapping for big drivers.


• Use the shielding for the more activated signal.


• Use the more decap cell near the sensitive circuit.


• Use of symmetisity in routing.


• For long routing use the higher metal layers.


• For the clock shielding put one side vcc and second side vss.


• Clock routing should be in upper metal layers.


these techniques are very use full for a good design .