SRAM

SRAM

 

Static Random Access Memory [SRAM]


Static Random Access Memory retains information placed within its cells until the values are overwritten or the power is switched off. Since SRAM doesn’t need to be refreshed constantly, reading and writing to memory can occur continuously. This allows it to be much faster than DRAM, which needs to pause between memory accesses to refresh and ensure that its contents are retained. Cache is much faster than main memory because it is implemented using SRAM

                                                                  Memory hierarchy

 



Basic six transistor SRAM memory cell






Pmos left side is M1 ,Nmos connected to bit line is M2,Nmos left side down is M3.


Pmos right side is M4 ,Nmos connected to bit line # is M5,Nmos right side down is M6.

(A) WRITE OPERATION:


When want to write 1 then bit line 1 and bit line# 0 will be apply . For this there may be 2 cases .


1) If node A having 1 and node b having 0 then


There will be very less current pass though M5 ( word line be on first) and node b will get discharge fully and create strong 0 . it will be depends upon the size of the m6 and m5 .


There will be very less current pass though M2 ( word line be on first ) and node a will be recharge again to strong 1 .


2) If node a having 0 and node b having 1 then


(B) READ OPERATION: for read operation both bit line and bit line # will be precharge to 1, then


1) if node a having 1 and node b having 0 then voltage of the bit line # will decrease this much the it will be less then weaker 1 (because of the M5 resistance it will not be fully discharge ) ,then difference between the bit line and bit line # is measured by the sense amplifier . Sense amplifier should be capable to measure this voltage difference. Timing of prechanging and sense amplifier should be different so there should not be short path between precharge and sense amplifier .




SIZING OF SRAM: sizing depends upon the technology used and the timing of the circuit required. Normally the sizes of the transistors are like M3 >M2 >M1.




Bit Line Precharge: used to precharge the bit line and bit line # before the read and write circuit . for this 3 pmos are used and connected at the same point so this circuit can provide strong 1 (pmos passes stronger 1 ).


Column Decoder Mux: use segmented mux to decode the address to the word lines .


Done many stage if address is big . domino logic can be used for fast speed.



Write driver circuitry : used to write the reuired bit on the memory node .


Sense Amplifier: important block for the reading operation . differential amplifier is used . sense amplifier amplified the low voltage difference between bit line and bit line #.


So reading speed is depends upon the sense amp.